1. Field of the Invention
The present invention relates to a technique for processing information, and particularly to a technique which can be effectively applied to, for example, an information processing system in which information is transmitted among a plurality of modules on a PCI_Express architecture and to a controlling technique thereof and the like.
2. Description of the Related Art
As an I/O connection interface for connecting an input/output device to a host device, the PCI_Express architecture has aroused interest. PCI_Express generally has a configuration as shown as conventional art in FIG. 1, in which a root complex 503 such as a memory bridge or the like for connecting a CPU 501 and memory 502 is connected to an upstream port 505 provided in a PCI_Express switch 504, and other input/output devices (End Point) 507 are connected to downstream ports 506 so that data transmission by packet routing between the upstream port 505 and the downstream ports 506 and among the downstream ports 506 is realized.
In a connection form utilizing the PCI_Express switch 504, port numbers for the downstream ports 506 are set using the single upstream port 505 as a reference, and packet routing is executed among ports using these port numbers as addresses.
The connection configuration shown in the above FIG. 1 shows a case for an information processing system of a relatively small scale such as a personal computer or the like. However, it is also possible that information processing devices which are on the same level as one another are connected respectively to the upstream port 505 and the downstream ports 506 of the PCI_Express switch 504.
In the above case, the same information processing devices are connected to all of the ports of the PCI_Express switch 504 i.e. the upstream port and all of the downstream ports.
In the above configuration, there is a problem such as the case that the information processing device connected to the upstream port is degraded (closed and degenerated) due to a hardware failure or the like.
Specifically, because configuration (setting of port numbers and the like) regarding the downstream ports in the PCI_Express switch 504 can be conducted only by the root complex of an upper level and via the upstream port, an information processing device which is always reliable has to be connected to the upstream port.
Accordingly, at a time when the information processing device connected to the upstream port is degraded, the setting of any one of the downstream ports 506 in the PCI_Express switch 504 has to be updated into the upstream port 505, and the port numbers of all of the ports have to be reset.
However, because the port numbers serving as the reference for packet routing are assigned by using the upstream port 505 as the reference as described above, each port number has to be reset at a time when a property of an arbitrary port is updated from downstream to upstream. The update of the setting is conducted by a maintenance interface or the like such as I2C or the like connected to the PCI_Express switch 504.
However, in an information processing system in which reliability is realized by a redundant connection of a plurality of information processing devices via the PCI_Express switch 504, in order to be basically operated for twenty four hours a day, the above described update of the setting of the PCI_Express switch 504 upon the occurrence of degradation of the upstream port has to be conducted when a power supply for the entire system is in an on state.
Accordingly, communications among ports other than the degraded port have to be stopped temporarily while the update of the setting of the PCI_Express switch 504 is conducted.
When a temporary stop of the communications among information processing devices via the PCI_Express switch 504 as above is conducted under the control of the firmware (software) of each information processing device, the update has to be conducted with the firmware (software) of each of the information processing devices in a state of synchronization, which leads to the technical problem of enormous complexity of the firmware algorithm.
With regard to a connection interface in an information processing device, Japanese Registered Utility Model No. 3091475 discloses a technique in which an input/output device connected to an USB interface is used in common by a plurality of hosts by connecting an upper level interface side of the USB interface to the plurality of the hosts via a multiplexer.
Also, Japanese Patent Application Publication No. 63-308685 discloses a technique in which a fault during a direct memory access operation is detected and when such a fault is detected, the direct memory access requests are masked by the lower level device side and a mask register the mask of which can only be cancelled by the central processing unit side after recovery from the fault is provided so that the plurality of the lower level devices are not affected by the fault occurring during the direct memory access operation, in a bus control device set between a system data bus on a central processing unit side and a local data bus on the lower level device side for conducting bus arbitration of the direct memory access.
Further, Japanese Patent Application Publication No. 2002-342255 discloses a technique in which a USB data converting device comprising a virtual USB host unit to which a plurality of USB devices are connected and a virtual USB device unit to which a plurality of USB hosts are connected is provided in an USB interface which basically assumes a connection configuration of “one to many” between the host and the USB devices, so that data transmission is realized between the plurality of USB hosts and the plurality of USB devices.
However, the above technical problem in the PCI_Express architecture is not recognized in any of the above conventional techniques.
[Patent Document 1]
    Japanese Registered Utility Model No. 3091475[Patent Document 2]    Japanese Patent Application Publication No. 63-308685[Patent Document 3]    Japanese Patent Application Publication No. 2002-342255